The invention relates to clock generator circuits. More particularly, the invention relates to a clock generator circuit that accepts phased input clock signals and provides from the phased input signals an output clock signal having low jitter and minimal delay.
Clock signals are used in virtually every digital integrated circuit (IC) and electronic system to control timing. For example, whenever there is a rising edge on a clock signal, all the flip-flops in a circuit may change state. Clearly, the higher the frequency of the clock signal, the faster the circuit operates. Therefore, much attention has been given to achieving the highest possible clock speeds that can be supported by the clock circuitry.
One problem that typically develops when high-frequency clocks are used is the problem of xe2x80x9cclock skewxe2x80x9d. Clock skew occurs when a clock signal is routed to two or more destinations and, because of varying delays on the clock paths, arrives at the targeted destinations at different times. For example, clock skew can occur when a clock signal is provided to the output pads and also to the internal circuitry of an IC. There might be, for example, a shorter delay in routing the clock signal to the output pads than there is in routing the clock signal to the internal circuitry. In this example, if the internal circuitry is driving the output pads, the clock skew can cause data errors.
A delay-lock loop (DLL) is often used to remove clock skew. A DLL corrects the difference in timing between two skewed clock signals by adding a delay to the slower path. The added delay is the additional delay required to give the slower path exactly one clock period more delay than the faster path. Thus, the two active edges arriving at the two target destinations are aligned, with one clock period of delay between the two clock signals.
DLLs are well known in the art of digital IC design. For example, one DLL is described by Nguyen in U.S. Pat. No. 6,373,308, entitled xe2x80x9cDirect-Measured DLL Circuit and Method,xe2x80x9d which is hereby incorporated by reference.
A typical DLL continuously monitors the relative delay between a feedback clock signal and an input (or reference) clock signal, adding an additional unit delay to the output clock signal when the feedback clock is too fast and subtracting a unit delay when the feedback clock is too slow.
Many DLLs provide phased output signals. For example, a DLL can provide both the original delayed clock signal and three other clock signals delayed by one-fourth, one-half, and three-fourths of a clock period from the original delayed clock signal.
Some DLLs also include clock generator circuits that provide other output clock signals. These output signals can include, for example, a 2xc3x97 clock having a clock frequency twice that of the input clock signal, or a divided clock signal having a clock frequency lower than that of the input clock signal. Divided clock signals can have, for example, clock frequencies divided by 1.5, 2.0, 2.5, 3.0, and so forth.
These output clock signals are typically generated by ring oscillators, and thus are subject to xe2x80x9cjitterxe2x80x9d (noise) caused by variations in temperature and/or power supply voltage. A feedback clock that includes jitter can cause a DLL to continuously adjust the number of unit delays on the clock path. These adjustments by the DLL themselves cause additional jitter on the clock signals provided by the DLL. Therefore, the DLL and oscillators form a system having a positive feedback loop in which the jitter can take a long time to settle down.
A conventional DLL reduces jitter by first pumping the power supply of the DLL to a higher level than the operating voltage, then regulating the power supply to minimize the effect of variations in IC power supply and temperature. Often, a large capacitor is also applied between the DLL power supply and ground. However, these methods are expensive in IC area and design complexity. Hence, they add significant cost to the final IC product and considerable time to the product development cycle.
Therefore, it is desirable to provide a clock generator circuit that can generate divided and/or multiplied clock signals having little or no jitter. It is further desirable to provide a clock generator circuit with minimal delay through the circuit.
The invention provides a clock generator circuit that accepts phased input clock signals having an input clock frequency, and generates from the phased signals an output clock signal having low jitter and a clock frequency created by dividing or multiplying the input clock frequency. In exemplary embodiments having four phased input signals and a duty cycle correction feature, the invention provides output clock frequencies of the input clock frequency divided by X/2, where X is an integer. In other embodiments not having duty cycle correction, the invention provides output clock frequencies of the input clock frequency divided by X/4. The delay through the clock generator circuit is less that that of known circuits, and is independent of the divisor.
In some embodiments, the output clock signal is shifted by 90, 180, or 270 degrees (one fourth, one half, or three quarters of a clock period) from the input clock signal. Other embodiments are programmable to provide various divisors and multipliers.
While the circuits of the invention can be used with phased input signals from any source, the circuit is particularly useful in conjunction with a delay-lock loop (DLL). In this context, the reduced jitter of the circuit of the invention provides a valuable advantage over known clock generator circuits, as it facilitates fast locking of the DLL. For example, in a programmable logic device (PLD), a programmable clock generator circuit according to the invention can be included in a DLL to provide a high level of versatility combined with fast locking capability.
A first embodiment of the invention provides a clock generator circuit comprising a state machine, a NOR circuit, a multiplexer, and a pulldown circuit. The state machine is driven by one of two or more phased input clock signals, and provides clock select signals to control the multiplexer circuit. The multiplexer circuit selects one of the phased input signals to pass to the output terminal of the clock generator. The clock select signals are also NORed together in the NOR circuit, and the output of the NOR circuit drives a pulldown on the output terminal.
Another embodiment includes two of the circuits described above, having two different state machines. One of the state machines provides a xe2x80x9csetxe2x80x9d signal that drives the output clock signal high, while the other state machine provides a xe2x80x9cresetxe2x80x9d signal that drives the output clock signal low. A xe2x80x9ckeeper circuitxe2x80x9d on the output terminal holds the output high after a set signal is received, and low after a reset signal is received. Thus, this embodiment provides duty cycle correction on the output clock signal.
Some embodiments of the invention are programmable. One such embodiment uses four phased input signals and includes a decoder circuit that decodes user code signals selecting a divisor from the group of 1.25, 1.5, 1.75, 7.75, 8. The decoder circuit provides control signals to the state machine that cause the state machine to implement the selected divisor. Another embodiment, which supports duty cycle correction and includes two state machines, permits a user to select a divisor from the group of 1.5, 2, 2.5, . . . , 7.5, 8. In this embodiment, each state machine can have its own decoder circuit, or the set and reset decoder circuits can be combined into a single decoder circuit.